In recent years, a new optical system as disclosed in Japanese Published Patent Application No. 2000-82226 has been developed with respect to a servo error generation circuit of an optical disc playback apparatus in order to increase accuracy of a servo error signal.
The above-mentioned literature discloses the technique of, with a sub beam receptor provided in addition to a main beam receptor, correcting a servo error signal obtained from the main beam receptor on the basis of the result of arithmetic operation performed on the output of the sub beam receptor. This technique prevents offset of a tracking error signal due to lens shift, and leakage of a track cross signal into a focus error signal.
Meanwhile, digitization of the servo error generation circuit has also been progressed, and the signal before the arithmetic operation of the servo error signal is generally AD (analog-to-digital) converted to perform servo error arithmetic processing by a digital circuit.
FIG. 10 is a block diagram illustrating the construction of a conventional servo error signal generation circuit in the case where a servo error signal is corrected by the above-mentioned method.
With reference to FIG. 10, the conventional servo error signal generation circuit is connected to a main-beam receptor 101 and a sub-beam receptor 102, and comprises an error signal 1F generator 103f, an error signal 2F generator 104f, an error signal 1T generator 103t, an error signal 2T generator 104t, switches 105a, 105b, 105c, and 105d, a sampling unit 106, an ADC (analog-to-digital converter) 107, registers 108f, 109f, 108t, and 109t, and adders 110f and 110t. 
The main-beam receptor 101 detects reflected light of a main beam from an optical disc. Further, the sub-beam receptor 102 detects reflected light of a sub beam from the optical disc, and detects a signal for assisting or correcting a detection signal from the main beam receptor 101.
The error signal 1F generator 103f operates the output of the main beam receptor 101 to output a focusing-side main error signal (Fmain), and the error signal 2F generator 104f operates the output of the sub beam receptor 102 to output a focusing-side sub error signal (Fsub).
Further, the error signal 1T generator 103t operates the output of the main beam receptor 101 to output a tracking-side main error signal (Tmain), and the error signal 2T generator 104t operates the output of the sub beam receptor 102 to output a tracking-side sub error signal (Tsub).
The sampling unit 106 performs switching among the switches 105a˜105d at a timing obtained by dividing a predetermined sampling period into four periods, and successively outputs, to the ADC 107, the signals outputted from the error signal 1F generator 103f, the error signal 2F generator 104f, the error signal 1T generator 103t, and the error signal 2T generator 104t. 
The ADC 107 is an AD converter for performing analog-to-digital conversion of an input signal.
The register 108f temporarily holds the output signal from the error signal 1F generator 103f, which has been AD-converted by the ADC 107. The register 109f temporarily holds the output signal from the error signal 2F generator 104f, which has been AD-converted by the ADC 107. The register 108t temporarily holds the output signal from the error signal 1T generator 103t, which has been AD-converted by the ADC 107. The register 109t temporarily holds the output signal from the error signal 2T generator 104t, which has been AD-converted by the ADC 107.
The adder 110f adds the output from the register 108f and the output from the register 109f to obtain a focus error signal output as an error signal output. Further, the adder 110t adds the output from the register 108t and the output from the register 109t to obtain a tracking error signal output as an error signal output.
Next, the operation will be described.
Initially, the error signal 1F generator 103f and the error signal 1T generator 103t, which have received the output signals from the main beam receptor 101, generate a Fmain signal and a Tmain signal, respectively. Further, the error signal 2F generator 104f and the error signal 2T generator 104t, which have received the output signals from the sub beam receptor 102, generate a Fsub signal and a Tsub signal, respectively.
Next, the four signals Fmain, Fsub, Tmain, and Tsub, which are generated by the error signal 1F generator 103f, the error signal 1T generator 103, the error signal 2F generator 104f, and the error signal 2T generator 104t, respectively, are successively output to the ADC 107 within a sampling period under switching control of the switches 105a to 105d by the sampling unit 106.
The ADC 107 performs AD conversion on the successively inputted signals. The AD-converted four signals Fmain, Fsub, Tmain, and Tsub are stored in the registers 108f, 109f, 108t, and 109t, respectively.
Thereafter, the adder 110f (110t) reads the data stored in the registers 108f and 109f (108t and 109t) at every sampling period, and calculates a servo error signal. Thereby, corrected focus error signal and tracking error signal are obtained for every sampling frequency fs.
Next, the operation of the sampling unit 106 will be described with reference to FIG. 11.
FIG. 11 is a timing chart for explaining the operation of the sampling unit 106.
As shown in FIG. 11, the sampling unit 106 performs switching control of the switches 105a to 105d, and successively outputs FM (Fmain) generated by the error signal 1F generator 103f, TM (Tmain) generated by the error signal 1T generator 103, FS (Fsub) generated by the error signal 2F generator 104f, and TS (Tsub) generated by the error signal 2T generator 104t, within the sampling period, in the order shown in FIG. 11.
Next, the operation of the conventional servo error detection circuit will be described with reference to a waveform diagram shown in FIG. 12.
FIG. 12 is a waveform diagram for explaining the operation of the conventional servo error detection circuit.
FIG. 12 shows, from top to bottom, a sampling timing (fs), a main error signal (main) as an output of the error signal 1F generator 103f or the error signal 1T generator 103t, a sub error signal (sub) as an output of the error signal 2F generator 104f or the error signal 2T generator 104t, an AD-converted output of the main error signal (main AD) stored in the register 108f or 108t, an AD-converted output of the sub error signal (sub AD) stored in the register 109f or 109t, and an error signal outputted from the adder 110f or 110t. 
The main error signal (main) and the sub error signal (sub) are sampled at the sampling timing fs by the sampling unit 106, thereby obtaining main AD and sub AD. Then, the main AD and the sub AD are added at every sampling timing fs, thereby obtaining an error signal in which an unnecessary noise component existing in the main error signal is corrected by the sub error signal.
In the conventional service error signal generation circuit, however, since the four signals including the main error signal and the sub error signal must be subjected to AD conversion within the sampling period as shown in FIG. 11, the conversion time of the AD converter must be equal to or shorter than ¼ of the sampling period, and a double-high conversion speed is required as compared with the case where only the main error signal is converted.
Further, when the processing speed of the AD converter is not sufficient, the sampling frequency must be reduced.